docs / xpu / llm

XPU index
  1. Overview
  1. One model, start to last token
  2. The scheduler: what runs when, beside what
  3. Optimization: what is decided when, and what is remembered
  4. Language models on the device: the cajeta-llm kernels
  5. Gradient boosting on the device: the cajeta-xgboost kernels
  6. Catalog: every cajeta-llm kernel
  7. Catalog: every cajeta-xgboost kernel

Math

  1. Overview

Nucleo

  1. Overview

ML

  1. Overview

LLM

  1. Overview
  2. Configuration
  3. Inside the engine
  4. Measuring, and where it stands
  5. Models and weight formats
  6. Quickstart
  7. Running and serving
  8. The engine API

Models and weight formats

What dev.cajeta.llm can load, and in which form.

1. Files

filehow it is read
a .gguf filethe GGUF metadata populates the model configuration; the tokenizer and the chat template come from the file
a .safetensors file, or a sharded .safetensors.index.jsonwith a Hugging Face config.json beside it (or named by the config option) and the tokenizer files of the repository

Checkpoint files are memory-mapped; a model is read once at load and the engine holds no second copy of the weights on the host.

2. Architectures

From GGUF, by the general.architecture key:

architecturenotes
llamaLlama 2 and 3.x, Mistral, Mixtral and the other Llama-shaped checkpoints; a mixture of experts is recognised by expert_count, not by the name
qwen2, qwen2vlthe text path of Qwen2 and Qwen2-VL
qwen2moeQwen2 mixture of experts, with the shared expert
qwen3Qwen3 dense, with QK-norm
qwen3moeQwen3 mixture of experts (Qwen3-Coder-30B-A3B is the measured reference)
bitnetternary BitNet checkpoints; a converter from the Hugging Face BitnetForCausalLM layout ships in the library

From Hugging Face config.json: LlamaForCausalLM and BitnetForCausalLM. A safetensors load carries no tokenizer, so it serves token-id submission and the converter (tools/convert/hf-to-gguf.sh) rather than text prompts. Grouped-query attention, rotary embeddings (the Llama-3.1 frequency table from rope_freqs.weight; linear, dynamic, YaRN and llama3 scaling from a Hugging Face configuration), sliding and per-layer windows, tied word embeddings, QK-norm, and the mixture-of-experts fields (expert count, active experts, the gated shared expert) are read from the configuration; nothing is assumed from the model’s name.

Gemma 3 is specified and deferred; it is not in this release.

3. Weight formats

Every format below has a host implementation, and a model whose format no device kernel serves still runs on the host. The device columns say which regimes have a dedicated kernel on the CUDA backend today; the catalog (every cajeta-llm kernel) has the row-by-row record for every backend, and Language models on the device describes the routes.

formatblockdecode (one row)batched decode (several sequences)prefill
f16f32-activation wave mat-vecf16 cooperative GEMM
Q4_0, Q5_032wave mat-vecint8 widen GEMM
Q4_1, Q5_132scalar mat-vecf16 cooperative GEMM
Q8_032wave mat-vecCols kernelint8 widen GEMM
Q2_K256wave mat-vecCols kernelint8 widen GEMM
Q3_K256wave mat-vecCols kernelint8 widen GEMM
Q4_K256wave mat-vec, prefetching twinCols kernel, fused q|k|v and gate|uptensor-core tile (QkTile); expert banks on the Id tile
Q5_K256wave mat-vecCols kerneltensor-core tile (Q5Tile); expert banks on the Q5 Id tile
Q6_K256wave mat-vec, prefetching twinCols kerneltensor-core tile (Q6Tile); expert banks on the multi-wave id GEMM
IQ2_XXS, IQ2_XS, IQ2_S, IQ3_XXS, IQ3_S256wave mat-vec (codebook)f16 cooperative GEMM
IQ4_NL, IQ4_XS32 / 256wave mat-vecf16 cooperative GEMM; IQ4_NL expert banks on the cooperative id GEMM
IQ1_S, IQ1_M256host decode
TQ1_0, TQ2_0 (ternary)256wave mat-vecf16 cooperative GEMM
MXFP432scalar mat-vec (a faster codebook variant exists and is not yet routed)

A checkpoint mixes formats (a Q5_K_M file holds Q5_K and Q6_K tensors and an f16 or Q8_0 output head), and the route is chosen per tensor. Activations are quantised on the device to q8_K for the integer routes.

4. Context and cache

The context length is an option (ctx, default 4096); the K/V cache is paged in blocks of blockTokens tokens (default 16) and shared across the sequences the scheduler runs. A file-backed prefix store (kvStore) keeps evicted blocks keyed by prefix hash, so a later request with the same prefix, or the same process after a restart, reuses them instead of recomputing.

Source: docs/xpu/llm/models.md · 3 min read · 728 words